View LTC695_196542.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC690/LTC691 LTC694/LTC695 Microprocessor Supervisory Circuits
FEATURES
s s s s
DESCRIPTIO
(R)
s s s
s s s
s s s
UL Recognized Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max.) Onboard Gating of RAM Chip Enable Signals SO-8 and SO-16 Packaging 4.65V Precision Voltage Monitor Power OK/Reset Time Delay: 50ms, 200ms, or Adjustable Minimum External Component Count 1A Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature Superior Upgrade for MAX690 Family
The LTC690 family provides complete power supply monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the Chip Enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V. The LTC690 family powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC690 family provides an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period.
APPLICATI
s s s s
S
Critical P Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems
TYPICAL APPLICATI
VIN 7.5V LT1086-5
+
10F
ADJ
100F
0.1F
LTC690/LTC691 LTC694/LTC695 VBATT RESET PFO PFI GND WDI 0.1F
0.1F
P SYSTEM P RESET P NMI I/O LINE 100
LTC690 TA1
RESET OUTPUT VOLTAGE (V)
VIN
VOUT
+5V
+
VCC
VOUT
POWER TO P CMOS RAM POWER
+3V 51k
10k MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS.
U
RESET Output Voltage vs Supply Voltage
5 TA = 25C EXTERNAL PULLUP = 10A VBATT = 0V 4 3 2 1 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5
LTC690 TA2
UO
UO
1
LTC690/LTC691 LTC694/LTC695 ABSOLUTE AXI U RATI GS (Notes 1 and 2)
VOUT Output Current .................. Short Circuit Protected Power Dissipation............................................. 500mW Operating Temperature Range LTC690/91/94/95C ............................... 0C to 70C LTC690/91/94/95I ............................ -40C to 85C Storage Temperature Range ................. -65C to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
Terminal Voltage VCC .................................................... -0.3V to 6.0V VBATT ................................................. -0.3V to 6.0V All Other Inputs ................... -0.3V to (VOUT + 0.3V) Input Current VCC .............................................................. 200mA VBATT ............................................................. 50mA GND .............................................................. 20mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VBATT VOUT VCC GND BATT ON LOW LINE OSC IN OSC SEL 1 2 3 4 5 6 7 8 LTC691 LTC695 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT
ORDER PART NUMBER LTC691CN LTC691IN LTC695CN LTC695IN
11 WDI 10 PFO 9 PFI
N PACKAGE 16-LEAD PLASTIC DIP
TJMAX = 110C, JA = 130C/W
TOP VIEW VOUT VCC GND 1 2 3 LTC690 LTC694 8 7 6 5 VBATT RESET WDI PFO
LTC690CN8 LTC690IN8 LTC694CN8 LTC694IN8
PFI 4
N8 PACKAGE 8-LEAD PLASTIC DIP
TJMAX = 110C, JA = 130C/W
PRODUCT SELECTIO GUIDE
PINS LTC690 LTC691 LTC694 LTC695 LTC699 LTC1232 LTC1235 8 16 8 16 8 8 16 RESET X X X X X X X WATCHDOG TIMER X X X X X X X BATTERY BACKUP X X X X POWER FAIL WARNING X X X X RAM WRITE PROTECT X X X X PUSHBUTTON RESET CONDITIONAL BATTERY BACKUP
2
U
U
W
WW
U
U
W
(Note 3)
TOP VIEW VBATT 1 VOUT 2 VCC 3 GND 4 BATT ON 5 LOW LINE 6 OSC IN 7 OSC SEL 8 LTC691 LTC695 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT 11 WDI 10 PFO 9 S PACKAGE 16-LEAD PLASTIC SOL PFI
ORDER PART NUMBER LTC691CS LTC691IS LTC695CS LTC695IS
TJMAX = 110C, JA = 130C/W Conditions: PCB mount on FR4 Material, Still Air at 25C, Copper Trace
TOP VIEW VOUT VCC GND PFI 1 2 3 4 LTC690 LTC694 8 7 6 5 VBATT RESET WDI PFO
S8 PART MARKING 690 690I 694 694I
LTC690CS8 LTC690IS8 LTC694CS8 LTC694IS8
S8 PACKAGE 8-LEAD PLASTIC SOIC
TJMAX = 110C, JA = 180C/W Conditions: PCB Mount on FR4 Material, Still Air AT 25C, Copper Trace
X
X
X
X
LTC690/LTC691 LTC694/LTC695
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, TA = 25C, unless otherwise noted.
PARAMETER Battery Backup Switching Operating Voltage Range VCC VBATT VOUT Output Voltage IOUT = 1mA
q
CONDITONS
MIN
TYP
MAX
UNITS
4.75 2.00 VCC - 0.05 VCC - 0.10 VCC - 0.50 VBATT - 0.1
q
5.50 4.25 VCC - 0.005 VCC - 0.005 VCC - 0.250 VBATT - 0.02 0.6 0.6 0.04 0.04 1.5 2.5 1 5 +0.02 +0.10 70 50 20 0.4 35
V V
IOUT = 50mA VOUT in Battery Backup Mode Supply Current (exclude IOUT) Supply Current in Battery Backup Mode Battery Standby Current (+ = Discharge, - = Charge) Battery Switchover Threshold VCC - VBATT Battery Switchover Hysteresis BATT ON Output Voltage (Note 4) BATT ON Output Short Circuit Current (Note 4) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time (LTC690/91) (Note 5) Reset Active Time (LTC694/95) (Note 5) Watchdog Timeout Period, Internal Oscillator OSC SEL HIGH, VCC = 5V
q q
IOUT = 250A, VCC < VBATT IOUT 50mA VCC = 0V, VBATT = 2.8V
q
V mA A A mV mV V m 25 4.75 60 70 240 280 2.00 2.25 120 140 4097 1025 A V mV ms ms sec ms Clock Cycles ms/V ms/V ns 200 0.4 mV V V
5.5 > VCC > VBATT + 0.2V
q
-0.1 -1.0
Power Up Power Down ISINK = 3.2mA BATT ON = VOUT Sink Current BATT ON = 0V Source Current 0.5 4.5 40 35 160 140 1.2 1.0 80 70 4032 960
1 4.65 40 50 50 200 200 1.6 1.6 100 100
OSC SEL HIGH, VCC = 5V
q
Long Period, VCC = 5V
q
Short Period, VCC = 5V
q
Watchdog Time-out Period, External Clock (Note 6) Reset Active Time PSRR Watchdog Time-out Period PSRR, Internal OSC Minimum WDI Input Pulse Width RESET Output Voltage At VCC = 1V RESET and LOW LINE Output Voltage (Note 4) RESET and WDO Output Voltage (Note 4)
Long Period Short Period
1 1 VIL = 0.4V, VIH = 3.5V ISINK = 10A, VCC = 1V ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1A, VCC = 5V ISINK = 1.6mA, VCC = 5V ISOURCE = 1A, VCC = 4.25V 3.5 0.4 3.5
q
200 4
3
LTC690/LTC691 LTC694/LTC695
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, TA = 25C, unless otherwise noted.
PARAMETER RESET, RESET, WDO, LOW LINE Output Short Circuit Current (Note 4) WDI Input Threshold WDI Input Current Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR PFI Input Current PFO Output Voltage (Note 4) PFO Short Circuit Source Current (Note 4) PFI Comparator Response Time (falling) PFI Comparator Response Time (rising) (Note 4) Chip Enable Gating CE IN Threshold CE IN Pullup Current (Note 7) CE OUT Output Voltage ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1A, VCC = 0V VCC = 5V, CL = 20pF
q
CONDITONS Output Source Current Output Sink Current Logic Low Logic High WDI = VOUT WDI = 0V VCC = 5V
q q
MIN 1
TYP 3 25
MAX 25 0.8
UNITS A mA V A
3.5 -50 1.25 4 -8 1.3 0.3 0.01 25 0.4 3.5 1 3 25 2 40 8 0.8 2.0 3 0.4 VOUT - 1.50 VOUT - 0.05 20 20 30 35 2 5 35 45 ns mA A V 25 A mA s s 50
q
1.35
V mV/V nA V
ISINK = 3.2mA ISOURCE = 1A PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT VIN = -20mV, VOD = 15mV VIN = 20mV, VOD = 15mV with 10k Pullup VIL VIH
V
CE Propagation Delay CE OUT Output Short Circuit Current Oscillator OSC IN Input Current (Note 7) OSC SEL Input Pullup Current (Note 7) OSC IN Frequency Range OSC IN Frequency with External Capacitor
Output Source Current Output Sink Current
A A 250 kHz kHz
OSC SEL = 0V OSC SEL = 0V, COSC = 47pF
q
0 4
The q denotes specifications which apply over the operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts or for the LTC692 and LTC693, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pullups of typically 3A. However, external pullup resistors may be used when higher speed is required. Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms (50ms typically) while the LTC694 and LTC695 have longer minimum
reset active time of 140ms (200ms typically). The reset active time of the LTC691 and LTC695 can be adjusted (see Table 2 in Applications Information Section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See BLOCK DIAGRAM). Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pullups which pull to the supply when the input pins are floating.
4
LTC690/LTC691 LTC694/LTC695
BLOCK DIAGRA W
M2 M1 VOUT CHARGE PUMP - C2 + LOW LINE + C1 - 1.3V BATT ON CE OUT GND CE IN - C3 PFI OSC IN OSC OSC SEL + PFO RESET RESET PULSE GENERATOR RESET WATCHDOG TIMER WDO
LTC690 BD
VBATT VCC
WDI
TRANSITION DETECTOR
PI FU CTIO S
VCC: +5V supply input. The VCC pin should be bypassed with a 0.1F capacitor. VOUT: Voltage output for backed up memory. Bypass with a capacitor of 0.1F or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical on resistance of 5. When VCC is lower than VBATT, VOUT is internally switched to VBATT. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Backup battery input. When VCC falls below VBATT, auxiliary power, connected to VBATT, is delivered to VOUT through PMOS witch, M2. If backup battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground pin. BATT ON: Battery on logic output from comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used.
U
U
U
5
LTC690/LTC691 LTC694/LTC695
PI FU CTIO S
PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. RESET: Logic output for P reset control. Whenever VCC falls below either the reset voltage threshold (4.65V, typically) or VBATT, RESET goes active low. After VCC returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 35ms for the LTC690 /1 (140ms for the LTC694/5). When the watchdog timer is enabled but not serviced prior to a preset time-out period, reset pulse generator also forces RESET to active low for a minimum of 35ms for the LTC690/1 (140ms for the LTC694/5) for every preset time-out period (see Figure 11). The reset active time is adjustable on the LTC691/5. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in Applications Information Section. RESET: RESET is an active high logic ouput. It is the inverse of RESET. LOW LINE: Logic output from comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.65V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1). WDI: Watchdog Input, WDI, is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11). WDO: Watchdog logic output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic input to the Chip Enable gating circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 5 for additional information. CE OUT: Logic output on the Chip Enable gating circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5). OSC SEL: Oscillator Selection input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low, allows OSC IN be driven from an external clock signal or external capacitor be connected between OSC IN and GND. OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see Applications Information Section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 50ms typical for the LTC691 and 200ms typical for the LTC695. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases, the time-out period immediately after a reset is 1.6 seconds typical.
6
U
U
U
LTC690/LTC691 LTC694/LTC695
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT vs IOUT
5.00 VCC = 5V VBATT = 2.8V TA = 25C 2.80 VCC = 0V VBATT = 2.8V TA = 25C
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.78 SLOPE = 125 2.76
PFI INPUT THRESHOLD (V)
4.95 4.90 SLOPE = 5 4.85
4.80
4.75
0
10
30 40 20 LOAD CURRENT (mA)
Reset Active Time vs Temperature LTC690-1
58 VCC = 5V 56
RESET VOLTAGE THRESHOLD (V)
RESET ACTIVE TIME
RESET ACTIVE TIME
54 52 50 48 46 -50 -25
0
50 25 75 TEMPERATURE (C)
Power Fail Comparator Response Time
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
6 5 4 3 2 1 0
VPFI 1.3V + - PFO 30pF
VCC = 5V TA = 25C
1.305V 1.285V 0 1
VPFI = 20mV STEP
2
345 TIME (s)
6
UW
50
LTC690 G1
VOUT vs IOUT
1.308 1.306 1.304 1.302 1.300 1.298 1.296 2.72
Power Failure Input Threshold vs Temperature
VCC = 5V
2.74
0
100
300 400 200 LOAD CURRENT (A)
500
LTC690 G2
1.294 -50 -25
0
50 25 75 TEMPERATURE (C)
100
125
LTC690 G3
Reset Active Time vs Temperature LTC694-5
232 VCC = 5V 224 216 208 200 192 184 -50 -25 4.65 4.64 4.63 4.62 4.61 4.66
Reset Voltage Threshold vs Temperature
100
125
0
50 75 25 TEMPERATURE (C)
100 125
LTC690 G5
4.60 -50 -25
0
50 25 75 TEMPERATURE (C)
100
125
LTC690 G4
LTC690 G6
Power Fail Comparator Response Time
6 5 4 3 2 1 0
VPFI 1.3V + - PFO 30pF
Power Fail Comparator Response Time with Pullup Resistor
6 5 4 3 2 1 0
+5V VPFI 1.3V + - PFO 10k 30pF
VCC = 5V TA = 25C
VCC = 5V TA = 25C
1.315V 1.295V 7 8
LTC690 G7
VPFI = 20mV STEP
1.315V 1.295V 0 2
VPFI = 20mV STEP
0
20 40
60 80 100 120 140 160 180 TIME (s)
LTC690 G8
4
6
8 10 12 14 16 18 TIME (s)
LTC690 G9
7
LTC690/LTC691 LTC694/LTC695
APPLICATI S I FOR ATIO U
the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold. Battery Switchover The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a charge pumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20s. During normal operation, the LTC690 family uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5. The VOUT pin should be bypassed with a capacitor of 0.1F or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC - VOUT voltage differential) is desired, the LTC691 and LTC695 should be used. These products provide BATT ON output to drive the base
V1 V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 t1 t1 = RESET ACTIVE TIME
LTC690 F1
Microprocessor Reset The LTC690 family uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 5% variation on VCC, so the RESET output becomes active low when VCC falls below 4.75V (4.65V typical). On power-up, the RESET signal is held active low for a minimum of 35ms for the LTC690/1 (140ms for the LTC694/5) after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC691/5. On powerdown, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the RESET output. Response time is typically 10s. To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1F capacitor with the leads trimmed as short as possible. The LTC691 and LTC695 have two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below
V2 VCC
RESET
t1
LOW LINE
8
W
U
UO
Figure 1. Reset Active Time
LTC690/LTC691 LTC694/LTC695
APPLICATI
S I FOR ATIO
of external PNP transistor (Figure 2). If higher currents are needed with the LTC690 and LTC694, a high current Schottky diode can be connected from the VCC pin to the VOUT pin to supply the extra current.
ANY PNP POWER TRANSISTOR
5 +5V 0.1F 1 +3V 3 BATT ON 2 VOUT VCC LTC691 LTC695 VBATT GND 4
LTC690 F2
0.1F
Figure 2. Using BATT ON to Drive External PNP Transistor
LTC690 F3
The LTC690 family is protected for safe area operation with short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long period of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155C with about 10C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC690 family uses a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by VBATT pin is strictly junction leakage. A 125 PMOS switch connects the VBATT input to VOUT in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is 1A maximum. The operating voltage at the VBATT pin ranges from 2.0V to 4.25V. High value capacitors, such as electrolytic or farad-
U
size double layer capacitors, can be used for short term memory backup instead of a battery. The charging resistor for both capacitors and rechargeable batteries should be connected to VOUT since this eliminates the discharge path that exists when the resistor is connected to VCC (Figure 3).
I= R +5V 0.1F VCC VOUT 0.1F VOUT - VBATT R LTC690 LTC691 LTC694 LTC695 +3V VBATT GND
W
U
UO
Figure 3. Charging External Battery Through VOUT
Replacing the Backup Battery When changing the backup battery with system power on, spurious resets can occur while battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC690 switches to battery backup. VOUT pulls VBATT low and the device goes back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1A maximum over temperature and the external resistor required to hold VBATT below VCC is:
V - 50mV R CC 1A
With VCC = 4.5V, a 4.3M resistor will work. With a 3V battery, this resistor will draw only 0.7A from the battery, which is negligible in most cases.
9
LTC690/LTC691 LTC694/LTC695
APPLICATI S I FOR ATIO U
OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor's address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC690 and LTC694 by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL VCC VOUT VBATT BATT ON PFI PFO RESET RESET STATUS C2 monitors VCC for active switchover. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1A maximum. Logic high. The open circuit output voltage is equal to VOUT. Power Failure Input is ignored. Logic low Logic low Logic high. The open circuit output voltage is equal to VOUT. LOW LINE Logic low WDI Watchdog Input is ignored. WDO CE IN CE OUT OSC IN OSC SEL Logic high. The open circuit output voltage is equal to VOUT. Chip Enable Input is ignored. Logic high. The open circuit output voltage is equal to VOUT. OSC IN is ignored. OSC SEL is ignored.
V1 V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS VOUT = VBATT
LTC690 F5
If battery connections are made through long wires, a 10 to 100 series resistor and a 0.1F capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4).
10 VBATT 4.3M 0.1F LTC690 LTC691 LTC694 LTC695 GND
LTC690 F4
Figure 4. 10/0.1F combination eliminates inductive overshoot and prevents spurious resets during battery replacement.
Table 1 shows the state of each pin during battery backup. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Memory Protection The LTC691 and LTC695 include memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is +5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE
VCC
CE IN
CE OUT VOUT = VBATT
10
W
U
UO
Figure 5. Timing Diagram for CE IN and CE OUT
LTC690/LTC691 LTC694/LTC695
APPLICATI
+5V 0.1F VCC LTC691 LTC695 CE OUT VBATT +3V GND CE IN RESET RESET TO P
LTC690 F6
S I FOR ATIO
+
10F 0.1F
VOUT
VCC 62512 RAM CS 20ns PROPAGATION DELAY FROM DECODER GND
Figure 6. A Typical Nonvolatile CMOS RAM Application
+5V 0.1F
VCC
VOUT
+
VCC 10F CS 0.1F 62128 RAM CS1 CS2 GND
LTC690 LTC694 VBATT RESET GND
+3V
Figure 7. Write Protect for RAM with LTC690 or LTC694
VIN 7.5V
LT1086-5 VIN VOUT ADJ +5V
+
10F R1 51k
+
VCC LTC690/LTC691 LTC694/LTC695 PFO PFI GND
100F R3 300k
0.1F R4 10k
R2 10k
TO P
LTC690 F8
Figure 8. Monitoring Unregulated DC Supply with the LTC690's Power Fail Comparator
VIN 6.5V
+
LT1086-5 VIN VOUT ADJ
10F
+5V R1 27k R4 10k R3 2.7M
0.1F VCC LTC690/LTC691 LTC694/LTC695 PFO PFI GND TO P
10F
+
R2 8.2k R5 3.3k
Figure 9. Monitoring Regulated DC Supply with the LTC690's Power Fail Comparator
U
Power Fail Warning The LTC690 family generates a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V several milliseconds before the +5V supply falls below the maximum reset voltage threshold 4.75V. PFO is normally used to interrupt the microprocessor to execute shut-down procedure between PFO and RESET or RESET. The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin. R1 R1 VH = 1.3V 1+ + R2 R3 When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction. R1 (5V - 1.3V)R1 VL = 1.3V 1 + - R2 1.3V(R3 + R4)
Assuming R4 << R3,VHYSTERESIS = 5V R1 R3
LTC690 F7
LTC1690 F09
W
U
UO
Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shut-down procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.5V which 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage
11
LTC690/LTC691 LTC694/LTC695
APPLICATI
S I FOR ATIO
of LT1086-5 (4.75V + 1.5V) and VHYSTERESIS = 850mV.
VHYSTERESIS = 5V R1 = 850V R3
+3V VBATT R1 1M PFI R2 1M
R3 5.88 R1 Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3. 51k (5V - 1.3V)51k 7.5V = 1.3V 1+ - R2 1.3 V(310 k) R2 = 9.7k, Choose nearest 5% resistor 10k and recalculate VL, 51k (5V - 1.3V)51k VL = 1.3V 1 + - = 7.32 V 1.3V(310k) 10k 51k 51k VH = 1.3V 1 + + = 8.151V 10k 300k
(7.32V - 6.25V) = 10.7ms 100mV/ms
VHYSTERESIS = 8.151V - 7.32V = 831mV The 10.7ms allows enough time to execute shut-down procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN. Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.85V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.
12
U
+5V VCC PFO LTC691 LTC695 CE IN CE OUT RL 20K OPTIONAL TEST LOAD GND I/O PIN LOW BATTERY SIGNAL TO P I/O PIN
LTC690 F10
W
U
UO
Figure 10. Backup Battery Monitor with Optional Test Load
Watchdog Timer The LTC690 family provides a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 35ms for the LTC690/1 (140ms for the LTC694/5). The reset active time is adjustable on the LTC691/5. Since many systems can not service the watchdog timer immediately after a reset, the LTC691 and LTC695 have longer time-out period (1.0 second minimum) right after a reset is issued. The normal time-out period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at 1.0 second minimum on the LTC690 and LTC694. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog time can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT.
LTC690/LTC691 LTC694/LTC695
APPLICATI S I FOR ATIO U
GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 35ms minimum for the LTC691 and 140ms minimum for the LTC695. OSC IN selectes between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second.
t1 = RESET ACTIVE TIME t2 = NORMAL WATCHDOG TIME-OUT PERIOD t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A RESET t3 t1
LTC690 F11
The LTC691 and LTC695 provide an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT. The LTC691 and LTC695 have two additonal pins OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and
VCC = 5V WDI
WDO
RESET t1
Figure 11. Watchdog Time-out Period and Reset Active Time
EXTERNAL CLOCK +5V 3 VCC OSC SEL 8 +5V 3 EXTERNAL OSCILLATOR VCC OSC SEL LTC691 LTC695 7 4 GND 7 OSC IN 8
LTC691 LTC695 4 GND
INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG +5V 3 VCC OSC SEL LTC691 LTC695 4 GND 7 FLOATING OR HIGH 4 8 FLOATING OR HIGH +5V 3
W
U
UO
t2
OSC IN
INTERNAL OSCILLATOR 100ms WATCHDOG VCC OSC SEL 8 FLOATING OR HIGH
LTC691 LTC695 GND OSC IN 7
OSC IN
Figure 12. Oscillator Configurations
LTC690 F12
13
LTC690/LTC691 LTC694/LTC695
APPLICATI
S I FOR ATIO
Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Time-out Selections
WATCHDOG TIME-OUT PERIOD OSC SEL OSC IN NORMAL (Short Period) Low Low Floating or High Floating or High External Clock Input External Capacitor* Low Floating or High 1024 clks 400ms xC 47pF 100ms 1.6 sec IMMEDIATELY AFTER RESET (Long Period) 4096 clks 1.6 sec xC 47pF 1.6 sec 1.6 sec RESET ACTIVE TIME
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is FOSC (Hz) =
Pushbutton Reset The LTC690 family does not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 100 resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1F capacitor to the RESET pin debounces the pushbutton input. The 100 resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC69X below ground. If a dedicated pushbutton reset input is desired, the LTC1235 is a good choice (Figure 14). It has all the functions of the LTC695 and provides pushbutton reset as an extra feature. Its pushbutton is internally debounced and invokes the normal 200ms reset sequence. This eliminates the need for the 100 resistor and 0.1F capacitor. It also provides a more consistent reset pulse.
+5V VCC RESET 0.1F 100 RESET MPU (e.g. 6805)
14
U
LTC691 LTC695 512 clks 200ms xC 47pF 50ms 50ms 184,000 C(pF) 2048 clks 800ms xC 47pF 200ms 200ms
LTC690/LTC691 LTC694/LTC695 GND
LTC690 F13
W
U
UO
Figure 13. The External Pushbutton Reset
+5V
VCC
RESET
RESET MPU (e.g. 6805)
LTC1235 PBRST GND
LTC690 F14
Figure 14. The External Pushbutton Reset with the LTC1235
LTC690/LTC691 LTC694/LTC695
TYPICAL APPLICATI
+5V
Capacitor Backup with 74HC4016 Switch
+5V VCC
0.1F R1 10k 1 R2 30k 10 11 12 14 74HC4016 7 13 100F 2 VBATT LTC691 LTC695 LOW LINE
+
PACKAGE DESCRIPTIO
0.300 - 0.320 (7.620 - 8.128)
N8 Package 8-Lead Plastic DIP
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 8.255 +0.635 -0.381
0.010 - 0.020 x 45 (0.254 - 0.508)
S8 Package 8-Lead Plastic SOIC
0- 8 TYP 0.016 - 0.050 0.406 - 1.270
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
U
UO
VCC
S
Write Protect for Additional RAMs
0.1F VOUT VCC 10F CE OUT VBATT +3V CE IN LOW LINE GND 0.1F VCC 62128 RAMB CS1 CS2 0.1F VCC 62128 RAMC CSC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs
LTC690 TA4
VOUT 0.1F
+
0.1F
LTC691 LTC695
62512 RAMA CS
20ns PROPAGATION DELAY CSA
GND
LTC690 TA3
CSB
Dimensions in inches (millimeters) unless otherwise noted.
0.400 (10.160) MAX 8 7 6 5
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN
0.250 0.010 (6.350 0.254)
)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
1
2
3
4
N8 0392
0.018 0.003 (0.457 0.076)
0.189 - 0.197 (4.801 - 5.004) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157 (3.810 - 3.988) 8 7 6 5
0.008 - 0.010 (0.203 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
S8 0392
1
2
3
4
15
LTC690/LTC691 LTC694/LTC695
PACKAGE DESCRIPTIO
0.300 - 0.325 (7.620 - 8.255)
0.130 0.005 (3.302 0.127)
0.009 - 0.015 (0.229 - 0.381)
0.015 (0.381) MIN
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.125 (3.175) MIN
0.291 - 0.299 (7.391 - 7.595) 0.005 (0.127) RAD MIN
0.010 - 0.029 x 45 (0.254 - 0.737)
0.093 - 0.104 (2.362 - 2.642)
0 - 8 TYP 0.050 (1.270) TYP
0.009 - 0.013 (0.229 - 0.330)
SEE NOTE 0.016 - 0.050 (0.406 - 1.270)
NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 1 2 3 4 5 6 7 8
SOL16 0392
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
U
Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead Plastic DIP
0.045 - 0.065 (1.143 - 1.651) 0.770 (19.558) MAX 16 15 14 13 12 11 10 9
0.065 (1.651) TYP
0.260 0.010 (6.604 0.254)
1 0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
2
3
4
5
6
7
8
N16 0492
SO Package 16-Lead SOL
0.398 - 0.413 (10.109 - 10.490) 0.037 - 0.045 (0.940 - 1.143) 16 15 14 13 12 11 10 9
0.004 - 0.012 (0.102 - 0.305)
SEE NOTE
0.394 - 0.419 (10.007 - 10.643)SOL16
0.014 - 0.019 (0.356 - 0.482) TYP
LT/GP 0692 5K REV B
(c) LINEAR TECHNOLOGY CORPORATION 1992

▲Up To Search▲

Price & Availability of LTC695

	To Download LTC695 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .